1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device including a data line pair to which differential data are transmitted and a semiconductor memory device.
2. Description of the Related Art
In general, a semiconductor memory device represented by DRAM includes more than tens of millions of memory cells for storing data, and stores or output data according to a command requested by a central processing unit such as a chip set. That is, when the chip set requests a write operation, data inputted through a data pad is transmitted through an input path and stored in a corresponding memory cell, and when the chip set requests a read operation, data stored in a corresponding memory cell is transmitted to a data pad through an output path and then outputted. Therefore, the semiconductor memory device includes input paths and output paths which are coupled to more than tens of millions of memory cells and configured to transmit data.
Meanwhile, the semiconductor memory device has developed according to the trend of large capacity, high speed, and miniaturization. In order to quickly process a large quantity of data in a state in which the chip size of the semiconductor memory device is gradually reduced, data lines composing the input and output paths should be efficiently controlled. For this operation, a variety of control methods are being currently researched. Hereafter, the present invention will be described in connection with a method for controlling such data lines.